In recent years, a huge demand for high-speed electronic devices creates an Electromagnetic Interference (EMI) issue in the applications of circuits and components. Since high speed electronic devices work under the condition of a high operating frequency relatively increase the level of electromagnetic interference, therefore a way of increasing the operating speed of a circuit while effectively lowering the electromagnetic interference demands immediate attentions and becomes a major issue to the circuit designers and manufacturers.
The prior art designs for resisting electromagnetic interference are mainly divided into the following two types:
1. Filtering Signals with High Electromagnetic Interference
It is rather impractical to filter the signals having high electromagnetic interference if it is necessary to operate in such a high operating frequency, since such arrangement also lowers the overall system performance. Although adding a metal shielding can reduce the high electromagnetic interference to a certain extent, yet its cost is too high for general practices.
2. Lowering Peak Energy of Clock Signal
The Frequency Modulation (FM) technology is used for lowering the peak energy in a clock signal. A standard clock signal is adopted for example. Referring to FIG. 1, a signal 102 indicates that when the energy level of a clock signal at a fundamental frequency is 100 MHz, the energy level is very close to the energy limit 104 specified by the Federal Communication Committee (FCC), and a signal 106 indicates that the energy level of a clock signal at a third harmonic frequency (3rd Harmonic) is 300 MHz, and a signal 108 indicates that the energy level of a clock signal at a fifth harmonic frequency (5th Harmonic) is 500 MHz.
However, after a frequency modulation is processed for the clock signal as shown in FIG. 1, the signal 102 is modulated to the signal 202 as shown in FIG. 2. The energy level of the signal 202 at the fundamental frequency is 100 MHz, and its frequency ranges from 99 MHz to 101 MHz, so that the energy level of the signal 202 is far below the energy limit 204 specified by the FCC. The signal 106 is modulated to the signal 206 as shown in FIG. 2. The energy level of the signal 206 at the third harmonic frequency is 300 MHz, and its frequency ranges from 297 MHz to 303 MHz. The signal 108 is modulated to the signal 208 as shown in FIG. 2. The energy level of the signal 208 at the fifth harmonic frequency is 500 MHz, and its frequency ranges from 495 MHz to 505 MHz. In FIGS. 1 and 2, the spectrum of the clock signal will be spread over after the frequency of the clock signal is modulated, and its spectrum is spread over within a wider frequency range to effectively lower its peak energy.
It is worth to point out that a very accurate modulation for the clock signal is needed; otherwise the center frequency of the modulated clock signal will be deviated far from the center frequency of the original clock signal. As a result, the recipient circuitry may be unable to operate normally due to the timing issue.
Sometimes users want to speed up their system to the greatest extent, they need the frequency of the system clock to be higher, so over clock is needed. In order to make the system work normally during over clock process and reach frequency as high as it can, it needs:    a. The over clock range must be large;    b. The clock frequency changes linearly, and the clock can maintain good performance during the over clock process;    c. There is no frequency overshoot at the end of the over clock process.
The prior art designs to produce spread spectrum and over clock are mainly divided into the following two types:
1. Using Integer Frequency Divider Charge Pump Phase Locked Loop
In recent years, an “integer frequency divider charge pump phase locked loop (PLL)” circuit is widely used in various different electronic devices for providing an accurate clock signal. Refer to FIG. 3 for a prior art integer frequency divider charge pump phase-locked loop 300, a divider 302 having a M divisor, a phase frequency detector (PFD) 304, a charge pump (CP) 306, a loop filter 318, a voltage controlled oscillator (VCO) 324, a divider 326 having a P divisor and a divider 328 having an N divisor.
The value of frequency of the output clock signal Fout of the integer frequency divider charge pump phase-locked loop 300 is equal to the multiplication of the input clock signal Fin and an N/(M×P) factor. Although the circuitry of such prior art integer frequency divider charge pump phase locked loop 300 provides a larger frequency range for the output clock signal Fout, the following shortcomings still exist, particularly for the high-speed electronic devices that use a higher frequency to achieve synchronization:    a. Since the factor M of the divider 302 is increased, the bandwidth of the phase locked loop 300 is decreased and its locking time is increased, and it cannot achieve high frequency resolution.    b. Overcharge occurs when the over clock ends.    c. The frequency change is nonlinear during the over clock process and thus causing excessively large phase noises and jitters or probably causing a system failure for receiving and using the clock signal at later stages.2. Using Decimal Frequency Division Phase Locked Loop
Referring to FIG. 4 for the prior art decimal frequency division phase locked loop, its circuitry is the same as the foregoing prior art integer frequency divider charge pump phase locked loop, except it has an additional K Bit accumulator 329 for controlling its N frequency divider to select the divisor factor as N or N−1 according to the input reference signal f to make the value of the frequency of its output clock signal Fout equal to
      F    in    ×  N  ×                    (                  1          +                      f                          2              k                                      )                    M        ×        P              .  Although the prior art decimal frequency division phase locked loop can achieve the high-frequency resolution and assure a wider bandwidth of the phase locked loop, yet it still has the following shortcomings:    a. The PLL has a narrow range of the output frequency.    b. A spur of decimal frequency division exists, and thus easily deteriorating phase noises.